| ISBN: ISBN: 0-7803-6546-1
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| ISBN: ISSN: 1089-3539
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| ISBN: DOI: 10.1109/TEST.2000.894197
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| |
| description |
We present the application of a deterministic logic BIST scheme on
state-of-the-art industrial circuits. Experimental results show that
complete fault coverage can be achieved for industrial circuits up
to 100K gates with 10,000 test patterns, at a total area cost for
BIST hardware of typically 5%-15%. It is demonstrated that a
trade-off is possible between test quality, test time, and silicon
area. In contrast to BIST schemes based on test point insertion no
modifications of the circuit under test are required, complete fault
efficiency is guaranteed, and the impact on the design process is
minimized.
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| publisher |
International Test Conference
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| type |
Text
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| Article in Proceedings
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| source |
In: Proceedings of the 31st IEEE International Test Conference
(ITC), Atlantic City, NJ, October 3-5, 200, pp. 105-114
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| contributor |
Rechnerarchitektur (IFI)
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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